The present invention relates generally to the field of data communications, and more particularly, to the field of serial communications bus controllers and microcontrollers that incorporate the same.
CAN (Control Area Network) is an industry-standard, two-wire serial communications bus that is widely used in automotive and industrial control applications, as well as in medical devices, avionics, office automation equipment, consumer appliances, and many other products and applications. CAN controllers are currently available either as stand-alone devices adapted to interface with a microcontroller or as circuitry integrated into or modules embedded in a microcontroller chip. Since 1986, CAN users (software programmers) have developed numerous high-level CAN Application Layers (CALs) which extend the capabilities of the CAN while employing the CAN physical layer and the CAN frame format, and adhering to the CAN specification. CALs have heretofore been implemented primarily in software, with very little hardware CAL support. Consequently, CALs have heretofore required a great deal of host CPU intervention, thereby increasing the processing overhead and diminishing the performance of the host CPU.
Thus, there is a need in the art for a CAN hardware implementation of CAL functions normally implemented in software in order to offload these tasks from the host CPU to the CAN hardware, thereby enabling a great savings in host CPU processing resources and a commensurate improvement in host CPU performance. One of the most demanding and CPU resource-intensive CAL functions is message management, which entails the handling, storage, and processing of incoming CAL/CAN messages received over the CAN serial communications bus and/or outgoing CAL/CAN messages transmitted over the CAN serial communications bus. CAL protocols, such as DeviceNet, CANopen, and OSEK, deliver long messages distributed over many CAN frames, which methodology is sometimes referred to as xe2x80x9cfragmentedxe2x80x9d or xe2x80x9csegmentedxe2x80x9d messaging. The process of assembling such fragmented, multi-frame messages has heretofore required a great deal of host CPU intervention. In particular, CAL software running on the host CPU actively monitors and manages the buffering and processing of the message data, in order to facilitate the assembly of the message fragments or segments into complete messages.
Based on the above and foregoing, it can be appreciated that there presently exists a need in the art for a hardware implementation of CAL functions normally implemented in software in order to offload these tasks from the host CPU, thereby enabling a great savings in host CPU processing resources and a commensurate improvement in host CPU performance.
The assignee of the present invention has recently developed a new microcontroller product, designated xe2x80x9cXA-C3xe2x80x9d, that fulfills this need in the art. The XA-C3 is the newest member of the Philips XA (eXtended Architecture) family of high performance 16-bit single-chip microcontrollers. It is believed that the XA-C3 is the first chip that features hardware CAL support.
The XA-C3 is a CMOS 16-bit CAL/CAN 2.0B microcontroller that incorporates a number of different inventions, including the present invention. These inventions include novel techniques and hardware for filtering, buffering, handling, and processing CAL/CAN messages, including the automatic assembly of multi-frame fragmented messages with minimal CPU intervention, as well as for managing the storage and retrieval of the message data, and the memory resources utilized therefor.
The present invention relates to a CAN microcontroller that supports a plurality (e.g., 32) of message objects, each one of which is assigned a respective message buffer within an on-chip and/or off-chip portion of the overall data memory space of the CAN microcontroller. The location and size of each of the message buffers can be reconfigured by the user (programmer) by simple programming of memory-mapped registers provided for this purpose. The message buffers are used to store incoming (receive) messages and to stage outgoing (transmit) messages. With the XA-C3 microcontroller that constitutes a presently preferred implementation of the present invention, Direct Memory Access (DMA) is employed to enable the XA-C3 CAN module to directly access any of the 32 message buffers without interrupting the processor core. This message storage scheme provides a great deal of flexibility to the user, as the user is free to use as much or as little message storage area as an application requires, and is also free to position the message buffers wherever it is most convenient.
This message storage scheme is a key element of the unique xe2x80x9cmessage managementxe2x80x9d capabilities of the XA-C3 CAN microcontroller, as this scheme enables the XA-C3 CAN/CAL module to concurrently assemble many (up to 32) incoming, fragmented messages of varying lengths, and, at the same time, stage multiple outgoing messages for transmission. Since incoming message assembly is handled entirely in hardware, the processor is free to perform other tasks, typically until a complete message is received and ready for processing.
The present invention encompasses a CAN microcontroller that supports a plurality of message objects, the CAN microcontroller including a processor core that runs CAN applications, a CAN/CAL module that processes incoming messages, and a plurality of message buffers associated with respective ones of the message objects, each message buffer having a size and a location that are programmable. The CAN microcontroller also includes a data memory space. Preferably, the plurality of message buffers are located in the data memory space, which may include both an on-chip portion and an off-chip portion.
The plurality of individual message object registers associated with each of the message objects contain fields of command/control information that facilitate configuration and setup of that message object. Preferably, the plurality of individual message object registers associated with each message object include at least one buffer size register that contains a message buffer size field that enables the size of the message buffer associated with that message object to be programmed, and at least one buffer location register that contains a message buffer location field that enables the location of the message buffer associated with that message object to be programmed.
In a presently preferred embodiment, the CAN microcontroller further includes a global message object register that contains a message buffer memory page field that defines a memory page within the data memory space in which all of the message buffers are located. Most preferably, the individual message object registers and the global message object register are implemented as memory-mapped registers, e.g., mapped to a dedicated RAM portion of the data memory space.
In the presently preferred embodiment, the CAN microcontroller also includes a DMA engine that enables the CAN/CAL module to directly access the message buffers without interrupting the processor core. Preferably, the DMA engine is contained within the CAN/CAL module.